dpretet/axi-crossbar
Parametric AXI4 crossbar in SystemVerilog
dpretet·1mo ago·May 15, 2026This release introduces support for any number of master and slaves agents and a wizard to generate it. The wizard is based on a JSON configuration file, and optionally a TUI to assist the user during generation. Add a script fix when launching the TUI.
dpretet·1mo ago·May 3, 2026This release introduces support for any number of master and slaves agents and a wizard to generate it. The wizard is based on a JSON configuration file, and optionally a TUI to assist the user during generation. **Full Changelog**: https://github.com/dpretet/axi-crossbar/compare/v1.1.1...v1.2.0
dpretet·9mo ago·August 26, 2025📋 Changes
- #20: Write completion could arrived before end of write channel last dataphase on misrouted transfer
- #9 : If a set of transactions using the same ID spanned over several masters, in-order ordering rule could be violated if masters completed transactions at different paces.
dpretet·9mo ago·August 25, 2025🐛 AXI4 Ordering Rules Fix
- This release is a major release for AXI ordering rule compliance. It addresses two major issues:
- #20: Write completion could arrived before end of write channel last dataphase on misrouted transfer
- #9: If a set of transactions using the same ID spanned over several masters, in-order ordering rule could be violated if masters completed transactions at different paces.
- Full Changelog: https://github.com/dpretet/axi-crossbar/compare/v1.0.3...v1.1.0
dpretet·1y ago·February 20, 2025Fix #21
dpretet·1y ago·November 26, 2024📋 Changes
- the core now keep last the granted master index
- the `en` control in slave and master switch have been updated
dpretet·2y ago·May 15, 2024This release addresses a clock issue around the master interface (from the internal switches to the external master interface). A wrong clock was connected, the issue affecting the core if `aclk` and `mstx_aclk` were different. It brings also details and corrections to the documentation. Any users using the CDC stages of the core must upgrade to this release.
dpretet·2y ago·March 30, 2024📋 Changes
- Update documentation to better explain ordering rules. States a master is not ensured to received in-order completion if use the same ID over different slaves
- Remove AXI3 backward compatibility by sizing ALOCK to a single bit. Locked accesses over the interconnect are no more supported
- Clean-up documentation
- Add IO/Parameter chapter
dpretet·4y ago·November 28, 2021📋 Changes
- Issue #5: Now the core can be can be configure to forbid some master to access particular slaves
- Issue #5: A master aiming to access an unmapped memory section receives a DECERR completion
- Issue #4: Add a new assertion to ensure MSTx_ID_MASK is not configured to 0 (unsupported value)
dpretet·4y ago·November 17, 2021📋 Changes
- Introduce a first decent documentation
- Fix an issue with AXI4-lite support if LAST were not tied to 1 on top interfaces
dpretet·4y ago·November 5, 2021First release, close to the final implementation. This version is fully usable but it doesn't implement yet timeout support and master routing. Still lack a decent documentation but the draw.io document contains figures describing the architecture.